VDC AND CIRCUITS ASSEMBLY LAUNCH 3D CHIP SCALE PACKAGING MULTI-CLIENT MARKET STUDY
02 June 2004 - Venture Development Corporation

Venture Development Corporation, a technology market research firm, and Circuits Assembly, a surface-mount and electronics assembly publication, are launching a multi-client market research study analyzing global market opportunities for 3D chip scale packaging solutions. Pre-publication sponsorship is available now.

This research program is based on extensive telephone interviews with suppliers, integrators, and other 3D packaging market participants. Key program deliverables will include:

Detailed market definitions and segmentations;

3D packaging technology descriptions;

Engineering approaches (thermal, power management, etc.);

Market estimates and forecasts across product categories and application segments;

Analysis of current and future applications;

OEM/integrator requirements and preferences;

Competitive position of 3D packaging component and solution suppliers; and

Lisa Bastin, Editor-In-Chief of Circuits Assembly, says, 'Although 3D chip scale packaging exceeds many performance demands and looks promising, there are still challenges that lie ahead such as cost and integration issues. We are excited to team with VDC to find answers to these issues and create a roadmap for the industry.'

Rick Barnard, Practice Director of VDC's Electronic Components and Advanced Materials group, says, 'As the technology landscape becomes more mobile-oriented and time-to-market challenges increase, system designers are faced with finding the optimal combination of form and function. This study will address important issues surrounding the 3D chip scale packaging opportunity by providing a granular, relevant market analysis with technical and developmental considerations.'

Circuits Assembly will be sharing with VDC their expertise of the industry to assist the research effort. Circuits Assembly's assistance will:

Enhance and further develop the contents and scope of the report, based on its knowledge of 3D chip scale packaging trends, business opportunities in the global market place, and innovations and technological developments in the industry; and

Bolster VDC's primary research program by queuing its massive proprietary database with VDC's research tools.

3D chip scale packaging refers to the vertical (Z-axis) stacking of multiple die within a package, or multiple packages, using specialized substrates and interconnects. Driven generally by wireless application markets, 3D chip scale packaging solutions will play a vital role in meeting performance and size requirements for future generations of mobile electronics. As portable products become smaller, lighter, and more feature-rich, the vertical stacking techniques employed in 3D chip scale packaging solutions will provide tremendous value by expanding and exceeding package miniaturization efforts to date, allowing increased functionality and reliability on the system level.

Circuits Assembly is a UP Media Group publication serving the surface-mount, mixed technology, and electronics assembly marketplace. The editorial mission of the magazine is to educate and inform electronics assemblers about the technologies in use today, and to prepare them for the changes in component packages, assembly methods and other processes expected in the future.

http://www.vdc-corp.com

More News:
  • For June 2004
  • From Venture Development Corporation
  • For Market Research