SEVERAL CHALLENGES LAY AHEAD FOR 3D CHIP SCALE PACKAGING SUPPLIERS
25 May 2004 - Venture Development Corporation

3D chip scale packaging solutions will play an increasingly vital role in meeting performance and size requirements for future generations of mobile electronics.

3D chip scale packaging refers to the vertical (Z-axis) stacking of multiple die within a package, or multiple packages, using specialized substrates and interconnects. Earlier advanced IC packaging solutions, such as ball grid array and chip scale package - have succeeded in decreasing package sizes while increasing I/O count and overall component performance, but their capabilities are falling short in today's more mobile-oriented technology landscape.

3D chip scale packaging solutions help to meet size and performance requirements by providing the following benefits:

Reductions of size and weight in the package - Vertical stacking reduces the number of chip-to-board interconnections and the area required for chips and inter-chip traces.

Reduction in power consumption - The level of power required depends in part on the number of interconnects. Currently, chip-to-chip interconnects account for 15-40% of power consumption. It is projected that Chip Scale Packaging and Multi-Chip Modules will reduce system power consumption by 10-30%.

Increase in performance and reliability - Currently, module-to-board solder connects account for 80-90% of board failures. Reducing the number of module-to-board solder connects by using 3D chip scale packaging will decrease board failures.

Although 3D chip scale packaging exceeds many performance demands, some challenges still exist. Mobile device manufacturers that VDC recently spoke to expressed their concerns about the viability of 3D chip scale packaging, including:

Expense - Products such as cell phones and other consumer devices have short product life cycles (1-2 years). The rapid turnover of new products and the hazy future of others (i.e. PDAs) create inconsistent demand for advanced packages. For applications that are in the mature or declining phases of their present life cycle, the additional costs of advanced packages are unjustified.

Changes to the supply chain - Cooperation between OEM system designers and their various suppliers must improve in order to address integration challenges.

Technology uncertainties - Board/system level manufacturers are concerned about reliability, ruggedness, power/thermal management, as well as shielding and other technical challenges.

As demands on portable devices increase and they become smaller, lighter and more feature-rich, the vertical stacking techniques employed in 3D chip scale packaging solutions may become more attractive to mobile device manufacturers. VDC provides insight into this emerging market by providing granular, relevant analysis of 3D chip scale packaging, including technical, developmental and commercialization considerations.

Since 1971, VDC has been a leading source of market research and consulting services for a host of electronic component and embedded technologies (CPU boards, chipsets, ASICs, and other discrete components), presenting granular and accurate market estimates, conservative forecasts, and relevant trend analyses through detailed market segmentations. VDC now turns its attention to the emerging 3D chip scale packaging market.

VDC and Circuits Assembly, a surface-mount and electronics assembly publication, are launching a multi-client market research study analyzing global market opportunities for 3D chip scale packaging solutions. Circuits Assembly will be sharing their expertise of the industry to assist the research effort. Circuits Assembly's assistance will:

Enhance and further develop the contents and scope of the report, based on its knowledge of 3D chip scale packaging trends, business opportunities in the global market place, and innovations and technological developments in the industry; and

Bolster VDC's primary research program by queuing its massive proprietary database with VDC's research tools.

This study will quantitatively and qualitatively assess market demand for components of 3D packaging technology, identify current and emerging applications, and evaluate strategies within the industry to address technical and marketing challenges. The report will include:

Detailed market definitions and segmentations;

3D packaging technology descriptions;

Engineering approaches (thermal, power management, etc.);

Market estimates and forecasts across product categories and application segments;

Analysis of current and future applications;

OEM/integrator requirements and preferences;

Competitive position of 3D packaging component and solution suppliers; and

Key success strategies.

VDC is now accepting founding sponsors for this research. Benefits of becoming a founding sponsor include:

Savings of up to $1,500

The opportunity to review and revise questionnaires

Updates during the research process alerting you to our interim findings, and

A personal presentation, schedule a time to meet with our analysts and probe for additional insights about your industry and market. VDC's study team will be available to present findings to any sponsor at their location of choice, subject to availability and client payment of travel expenses.

http://www.vdc-corp.com

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